FIG. 5 shows, in a perspective view, the appearance of a ceramic electronic component 1 of interest to this disclosure. The ceramic electronic component 1 includes a chip-shaped ceramic body 2. The ceramic body 2 has a cuboid shape that has a profile defined by four side surfaces 3, 4, 5, and 6 and two end surfaces 7 and 8.
Although not shown, in the ceramic body 2, an internal conductor is provided in a form depending on the function of the ceramic electronic component 1. For example, when the ceramic electronic component 1 is a coil component, a coil conductor is provided in the ceramic body 2, and when the ceramic electronic component 1 is a multilayer ceramic capacitor, multiple sets of internal electrodes opposed to each other are provided therein.
External electrodes 9 and 10 electrically connected to the internal conductor mentioned above are formed on the ceramic body 2. At least parts for each of the external electrodes 9 and 10, that is, surface layers for each of the external electrodes 9 and 10 in the example shown, are provided by plated films 11 and 12 formed by electrolytic plating.
For the formation of the plated films 11 and 12, although not shown, seed electrodes to serve as starting points for plating growth are formed to constitute bases for plated films 13 and 14.
The seed electrodes are, for example, as described in JP 11-67554 A, provided by end-surface base electrodes formed by baking a conductive paste on the end surfaces 7 and 8 of the ceramic body 2, or when the ceramic body 2 has a laminated structure composed of a plurality of ceramic layers, provided by side-surface base electrodes obtained by partially exposing, at side surfaces 3 to 6 electrode layers formed between the ceramic layers.
In the case of the foregoing ceramic electronic component 1, the respective locations of end edges 13 and 14 for each of the plated films 11 and 12 that provide the surface layers of the external electrodes 9 and 10 are determined depending on how the plated films 11 and 12 each undergo plating growth along the side surfaces 3 to 6. More specifically, in the case of the plated film 11 formed on the end surface 7, the location of the end edge 13 is determined depending on how plating grows along the side surfaces 3 to 6 toward the opposed end surface 8. In the case of the plated film 12 formed on the end surface 8, the location of the end edge 14 is determined depending on how plating grows along the side surfaces 3 to 6 toward the opposed end surface 7. To the degree of plating growth along the side surfaces 3 to 6, that is, a plating growth dimension L, the end of the plating growth is important, rather than the beginning of the plating growth.
The factors that determine the plating growth dimension L mentioned above include the charge amount (current value×plating time) applied in electrolytic plating. Therefore, conventionally, the applying charge amount for obtaining an intended plating growth dimension L is set for each product to be manufactured, and electrolytic plating is carried out by applying the set charge amount while the product is manufactured. However, the change in product lot even for the same product may also cause the plating growth dimension L1 to vary between product lots. More specifically, the plating growth dimension L varies between product lots.
The plating growth dimension L preferably varies as little as possible between product lots. This is because the variation in plating growth dimension L may cause the ceramic electronic component 1 to vary in characteristics. For example, when the ceramic electronic component 1 is a coil component, the excessively large plating growth dimension L may increase the degree of interference between the magnetic flux formed by a coil and the plated films 11 and 12, thereby affecting the characteristics of the ceramic electronic component 1. In addition, the variation in plating growth dimension L may cause defective appearances.
Further, methods for controlling the plating growth dimension L include the method described in JP 7-90675 A. JP 7-90675 A mentions a technique of appropriately setting up the pulse current condition for a pulsed power supply with the use of the pulsed power supply for plating an electronic component, thereby making it possible to control a plating growth dimension.
However, the technique mentioned in JP 7-90675 A is not suitable for reducing the variation in plating growth dimension between product lots. According to the technique mentioned in JP 7-90675 A, a pulse control parameter (cutoff value) for an electric current to be supplied is determined on the basis of an intended plating growth dimension, thereby only carrying out plating based on the cutoff value, but the plating growth dimension is not predicted for each product lot, or the correction for obtaining the intended plating growth dimension from the predicted plating growth dimension is not made to the pulse current condition for the pulsed power supply.